1. Field of the Invention
The present invention relates to a charge pump circuit, and more particularly to a charge pump circuit transferring positive electric charge or negative electric charge of an input node to an output node in synchronization with a clock signal.
2. Description of the Background Art
Conventionally, a flash memory includes a positive charge pump circuit and a negative charge pump circuit to generate a high voltage for data writing and data erasing (see FIG. 1).
FIGS. 19A to 19C are circuit block diagrams showing a structure of a conventional positive charge pump circuit.
In FIG. 19A, the positive charge pump circuit includes an N channel MOS transistor 101 and N (where N is an even number) stage charge pump unit circuits 102.1-102.N connected in series. N channel MOS transistor 101 is diode connected between a line of power supply potential VCC and an input node of charge pump unit circuit 102.1 of the first stage.
Charge pump unit circuits 102.1, 102.3, . . . , 102.Nxe2x88x921 located at odd-numbered stages supply positive charge to charge pump unit circuits 102.2, 102.4, . . . , 102.N located next to them, respectively, in synchronization with clock signals CLK11 and CLK12. Charge pump unit circuits 102.2, 102.4, . . . , 102.N located at even-numbered stages supply positive charge to charge pump unit circuits 102.3, 102.5, . . . , 102.Nxe2x88x921 located next to them and to an output node, respectively, in synchronization with clock signals CLK13 and CLK14. An output potential of charge pump unit circuit 102.N of the last stage is an output potential VO of the positive charge pump circuit.
Charge pump unit circuit 102.1 includes an N channel MOS transistor 103, a resistance element 104, and capacitors 105 and 106 as shown in FIG. 19B. N channel MOS transistor 103 is connected between an input node N102 and an output node N103 of charge pump unit circuit 102.1. Resistance element 104 is connected between a gate of N channel MOS transistor 103 and an input node N102. Capacitor 105 has one electrode receiving clock signal CLK11 and another electrode connected to input node N102. Capacitor 106 has one electrode receiving clock signal CLK12 and another electrode connected to the gate of N channel MOS transistor 103.
Charge pump unit circuits 102.3, 102.5, . . . , 102.Nxe2x88x921 of odd-numbered stages are each of the same structure with charge pump unit circuit 102.1. Charge pump unit circuit 102.2, 102.4, . . . , 102.N of even-numbered stages are each same with charge pump unit circuit 102.1 except that clock signals CLK13 and CLK14 are employed instead of clock signals CLK11 and CLK12 as shown in FIG. 19C.
FIGS. 20A-20D are waveform diagrams of clock signals CLK11-CLK14. FIG. 21 is a schematic waveform diagram of a potential VI of input node N102, a gate potential VG of N channel MOS transistor 103, and potential VO of output node N103 in each of charge pump unit circuits 102.1, 102.3, . . . , 102.Nxe2x88x921 of odd-numbered stages. Next, an operation of the positive charge pump circuit will be described with reference to FIGS. 20A-20D and FIG. 21.
First, with reference to FIGS. 20A-20D, clock signal CLK11 has a predetermined period and its duty factor is 50%. In FIGS. 20A-20D, clock signal CLK11 attains an xe2x80x9cHxe2x80x9d level (a logical high level) from t1 to t3 and from t5 to t7, whereas attains an xe2x80x9cLxe2x80x9d level (a logical low level) from t3 to t5. Each of clock signals CLK12 to CLK14 has the same period as clock signal CLK11. Clock signal CLK12 attains an xe2x80x9cHxe2x80x9d level in the latter half (that is, t2-t3 and t6-t7) of a time period during which clock signal CLK11 is atan xe2x80x9cHxe2x80x9d level and attains an xe2x80x9cLxe2x80x9d level in other time period. Clock signals CLK13 and CLK14 are a half period delayed from clock signals CLK11 and CLK12, respectively.
Before t1, clock signals CLK11 and CLK12 are both at an xe2x80x9cLxe2x80x9d level. Therefore, VI and VG are both atan xe2x80x9cHxe2x80x9d level and capacitors 105 and 106 are charged with power supply voltage VCC.
At t1, clock signal CLK11 is turned from an xe2x80x9cLxe2x80x9d level to an xe2x80x9cHxe2x80x9d level. Then the potential on input node N102 is boosted by an amount of power supply voltage VCC via capacitor 105 and the boosted potential VI on input node N102 is transferred to a gate of N channel MOS transistor 103 via resistance element 104. Gate potential VG rises according to a curve determined by a time constant of the circuit.
At t2, clock signal CLK12 is turned from an xe2x80x9cLxe2x80x9d level to an xe2x80x9cHxe2x80x9d level. Then gate potential VG is boosted by an amount of power supply voltage VCC via capacitor 106. As a resistance of N channel MOS transistor 103 decreases, positive charge is transferred from input node N102 to output node N103, whereby input potential VI falls and output potential VO rises.
At t3, clock signals CLK11 and CLK12 are turned from an xe2x80x9cHxe2x80x9d level to an xe2x80x9cLxe2x80x9d level. Thus the states of the signals return to the states before t1.
During the time period from t3 to t5, clock signals CLK11 and CLK12 are held atan xe2x80x9cLxe2x80x9d level and charge pump unit circuits 102.1, 102.3, . . . , 102.Nxe2x88x921 of odd-numbered stages do not operate. During the time period from t3 to t5, charge pump unit circuits 102.2, 102.4, . . . , 102.N of even-numbered stages operate in the same manner as charge pump unit circuits 102.1, 102.3, . . . , 102.Nxe2x88x921 of odd-numbered stages from t1 to t3.
Thus in the positive charge pump circuit, charge pump unit circuits 102.1, 102.3, . . . , 102.Nxe2x88x921 of odd-numbered stages and charge pump unit circuits 102.2, 102.4, . . . , 102.N of even-numbered stages alternately operate in synchronization with clock signals CLK11 to CLK14. Positive charge is supplied from each charge pump unit circuit to a charge pump unit circuit of the next stage. Positive charge is boosted in each charge pump unit circuit and charge pump unit circuit 102.N of the final stage outputs a positive potential VO of a high level.
FIGS. 22A-22C are circuit block diagrams showing a structure of a conventional negative charge pump circuit.
In FIG. 22A, the negative charge pump circuit includes a P channel MOS transistor 111 and N stages of charge pump unit circuits 112.1 to 112.N connected in series. P channel MOS transistor 111 is diode connected between an input node of charge pump unit circuit 112.1 of the first stage and a line of a ground potential VSS.
Charge pump unit circuits 112.1, 112.3, . . . , 112.Nxe2x88x921 of odd-numbered stages supply negative charge to charge pump unit circuits 112.2, 112.4, . . . , 112.N located next to them, respectively, in synchronization with clock signals CLK31 and CLK32. Charge pump unit circuits 112.2, 112.4, 112.Nxe2x88x922 of even-numbered stages supply negative charge to charge pump unit circuits 112.3, 112.5, . . . , 112.Nxe2x88x921 located next to them and to an output node, respectively, in synchronization with clock signals CLK33 and CLK34. An output potential of charge pump unit circuit 112.N of the last stage is an output potential VO of the negative charge pump circuit.
Charge pump unit circuit 112.1 includes a P channel MOS transistor 113, a resistance element 114, and capacitors 115 and 116 as shown in FIG. 22B. P channel MOS transistor 113 is connected between an input node N112 and an output node N113 of charge pump unit circuit 112.1. Resistance element 114 is connected between a gate of P channel MOS transistor 113 and input node N112. Capacitor 115 has one electrode receiving clock signal CLK31 and another electrode connected to input node N112. Capacitor 116 has one electrode receiving clock signal CLK32 and another electrode connected to the gate of N channel MOS transistor 113.
Other charge pump unit circuits 112.3, 112.5, . . . , 112.Nxe2x88x921 of odd-numbered stages are each of the same structure with charge pump unit circuit 112.1. Charge pump unit circuits 112.2, 112.4, . . . , 112.N of even-numbered stages are each same with charge pump unit circuit 112.1 except that clock signals CLK33 and CLK34 are employed instead of clock signals CLK31 and CLK32 as shown in FIG. 22C.
FIGS. 23A to 23D are waveform diagrams of clock signals CLK31 to CLK34. FIG. 24 is a schematic waveform diagram of a potential VI of input node N112, a gate potential VG of P channel MOS transistor 113, and a potential VO of output node N113 in each of charge pump unit circuits 112.1, 112.3, . . . , 112.Nxe2x88x921 of odd-numbered stages. Next, an operation of the negative charge pump circuit will be described with reference to FIGS. 23A to 23D and FIG. 24.
First, with reference to FIGS. 23A to 23D, clock signal CLK31 has a predetermined period and the duty factor is 50%. In FIGS. 23A to 23D, clock signal CLK31 attains an xe2x80x9cLxe2x80x9d level from t1 to t3 and attains an xe2x80x9cHxe2x80x9d level from t3 to t5. Each of other clock signals CLK32 to CLK34 has the same period as clock signal CLK31. Clock signal CLK32 attains an xe2x80x9cLxe2x80x9d level at the latter half (t2-t3) of a time period during which clock signal CLK31 is atan xe2x80x9cLxe2x80x9d level, and is atan xe2x80x9cHxe2x80x9d level in other time period. Clock signals CLK33 and CLK34 are half period delayed from clock signals CLK31 and CLK32, respectively.
Before t1, clock signals CLK31 and CLK32 are both atan xe2x80x9cHxe2x80x9d level. Therefore, VI and VG are both atan xe2x80x9cLxe2x80x9d level and capacitors 115 and 116 are charged with a power supply voltage xe2x88x92VCC.
At t1, clock signal CLK31 is turned from an xe2x80x9cHxe2x80x9d level to an xe2x80x9cLxe2x80x9d level. Then the potential of input node N112 is lowered by an amount of power supply voltage VCC via capacitor 115 and the lowered potential VI on input node N112 is transferred to the gate of N channel MOS transistor 113 via resistance element 114. Gate potential VG falls according to a curve determined by a time constant of the circuit.
At t2, clock signal CLK32 is turned from an xe2x80x9cHxe2x80x9d level to an xe2x80x9cLxe2x80x9d level. Then gate potential VG is lowered by an amount of power supply voltage VCC via capacitor 116. As a resistance of P channel MOS transistor 113 decreases, negative charge is transferred from input node N112 to output node N113, whereby input potential VI rises and output potential VO falls.
At t3, clock signals CLK31 and CLK32 are turned from an xe2x80x9cLxe2x80x9d level to an xe2x80x9cHxe2x80x9d level. Thus the states of the signals return to the states before t1.
During the time period from t3 to t5, clock signals CLK31 and CLK32 are held atan xe2x80x9cHxe2x80x9d level and charge pump unit circuits 112.1, 112.3, . . . , 112.Nxe2x88x921 of odd-numbered stages do not operate. During the time period from t3 to t5, charge pump unit circuits 112.2, 112.4, . . . , 112.N of even-numbered stages operate in the same manner as charge pump unit circuits 112.1, 112.3, . . . , 112.Nxe2x88x921 of odd-numbered stages from t1 to t3.
Thus in the negative charge pump circuit, charge pump unit circuits 112.1, 112.3, . . . , 112.Nxe2x88x921 of odd-numbered stages and charge pump unit circuits 112.2, 112.4, . . . , 112.N of even-numbered stages alternately operate in synchronization with clock signals CLK31 to CLK34. Negative charge is supplied from each charge pump unit circuit to a charge pump unit circuit of the next stage. Negative charge is decreased in each charge pump unit circuit and charge pump unit circuit 112.N of the final stage outputs a negative potential VO of a high level.
With the introduction of a low power supply voltage in semiconductor devices, flash memories are also required to operate at a low power supply voltage. Flash memories include charge pump circuits for generating a high voltage as described above. When power supply voltage is lowered (especially when it becomes lower than 2V), however, the generation of high voltage becomes difficult in the conventional charge pump circuit.
In the positive charge pump circuit shown in FIGS. 19A to 19C, the condition VGxe2x88x92VO greater than Vthn (where Vthn is the threshold voltage of N channel MOS transistor 103) must be satisfied in order to render N channel MOS transistor 103 conductive. As Vthn increases towards the final stage because of a so-called substrate effect, the conduction of N channel MOS transistor 103 becomes hard to establish. Thus the positive charge cannot efficiently be transferred to the next stage.
Similarly, in the negative charge pump circuit shown in FIGS. 22A to 22C, the condition VGxe2x88x92VO less than Vthp (where Vthp is the threshold voltage of P channel MOS transistor 113) must be satisfied in order to render P channel MOS transistor 113 conductive. As Vthp increases towards the final stage because of a so-called substrate effect, the conduction of P channel MOS transistor 113 becomes hard to establish. Thus the negative charge cannot efficiently be transferred to the next stage.
Therefore, a main object of the present invention is to provide a charge pump circuit allowing an efficient transfer of electric charge.
According to one aspect of the present invention, the charge pump circuit transferring positive charge or negative charge of an input node to an output node in synchronization with a clock signal, includes a first transistor of a first conductivity type connected between the input node and the output node; a second transistor of a second conductivity type connected between the input node and an input electrode of the first transistor; a first driving circuit pulling down or pulling up a potential of the input node by an amount of a first voltage during a first time period of each period of the clock signal; a first switching circuit turning the second transistor non conductive by connecting an input electrode of the second transistor and the input electrode of the first transistor during a second time period in the first time period and turning the second transistor conductive by supplying an activation potential to the input electrode of the second transistor during a time period other than the second time period; and a second driving circuit turning the first transistor conductive by pulling up or pulling down a potential of the input electrode of the first transistor by an amount of a second voltage during a third time period in the second time period. Therefore, dissimilar to the conventional device where a resistance element is connected between the input node and the input electrode of the first transistor, positive or negative charge of the input electrode of the first transistor does not flow back to the input node at the rise and the fall of a potential of the input electrode of the first transistor. Thus, the resistance of the first transistor can be reduced and the efficient charge transfer is allowed.
Preferably, the first voltage is a power supply voltage; the second voltage is higher than the power supply voltage; and the second driving circuit includes an amplitude converting circuit receiving a reference clock signal being at a first potential during the third time period and at a second potential during a time period other than said third time period, and having an amplitude equal to the power supply voltage, and converting the amplitude of the reference clock signal to the second voltage and supplying the result as an output, and a first capacitor having one electrode receiving an output clock signal of the amplitude converting circuit and another electrode connected to the input electrode of the first transistor. In this case, the resistance of the first transistor can be further reduced and the even more efficient charge transfer is allowed.
Still more preferably, the second voltage is twice as high as the power supply voltage, and the amplitude converting circuit includes, a second capacitor, a charge circuit charging the second capacitor to the level of power supply voltage by supplying power supply potential to one electrode of the second capacitor and supplying a ground potential to another electrode of the second capacitor during a time period in which the reference clock signal is at the second or first potential, and a second switching circuit supplying the power supply potential to another electrode of the second capacitor charged by the charge circuit and connecting one electrode of the second capacitor to one electrode of the first capacitor in a time period in which the reference clock signal is at the first or second potential, and supplying the ground potential to one electrode of the first capacitor during a time period in which the reference clock signal is at the second or first potential. In this case, the potential of the input electrode of the first transistor can be increased or decreased by an amount corresponding to twice the power supply voltage. Hence the resistance of the first transistor can sufficiently be lowered.
Still more preferably, the amplitude converting circuit includes, an internal charge pump circuit supplying positive charge to an internal power supply node, a control circuit controlling the internal charge pump circuit so as to turn a potential of the internal power supply node to a predetermined reference potential, and a second switching circuit connecting one electrode of the first capacitor to the internal power supply node during a time period in which the reference clock signal is at the first or second potential and supplying the ground potential to one electrode of the first capacitor during a time period in which the reference clock signal is at the second or first potential. In this case, the potential of the input electrode of the first transistor can be increased or decreased by a desired amount by setting the reference potential at a desired level. Hence, the resistance of the first transistor can sufficiently be lowered.
According to another aspect of the present invention, the charge pump circuit transferring positive charge or negative charge of an input node to an output node in synchronization with a clock signal, includes: a transistor connected between the input node and the output node; a resistance element connected between the input node and an input electrode of the transistor; a first driving circuit pulling down or pulling up a potential of the input node by an amount of a power supply voltage during a first time period of each period of the clock signal; and a second driving circuit turning the transistor conductive by pulling up or pulling down a potential of the input electrode of the transistor by an amount of a predetermined voltage higher than the power supply voltage during a second time period in the first time period. The second driving circuit includes an amplitude converting circuit receiving a reference clock signal being at a first potential during the second time period and at a second potential during a time period other than said second time period and having an amplitude equal to the power supply voltage, and, converting the amplitude of the reference clock signal to the predetermined voltage and supplying the result as an output, and a first capacitor having one electrode receiving an output clock signal of the amplitude converting circuit and another electrode connected to the input electrode of the transistor. Therefore, the resistance of the transistor can be reduced compared with the conventional device where the potential of the input electrode of the transistor is increased or decreased solely by the power supply voltage and electric charge can efficiently be transferred.
According to still another aspect of the present invention, the charge pump circuit transferring positive charge or negative charge of an input node to an output node in synchronization with a clock signal, includes: a transistor connected between the input node and the output node; a diode element connected between the input node and an input electrode of the transistor; a first driving circuit pulling down or pulling up a potential of the input node by an amount of power supply voltage during a first time period of each period of the clock signal; and a second driving circuit turning the transistor conductive by pulling up or pulling down a potential of the input electrode of the transistor by an amount of a predetermined voltage higher than the power supply voltage during a second time period in the first time period. The second driving circuit includes an amplitude converting circuit receiving a reference clock signal having the same period with the clock signal, being at a first potential during the second time period of each period and at a second potential during a time period other than said second time period and having an amplitude equal to the power supply voltage, and, converting the amplitude of the reference clock signal to the predetermined voltage and supplying the result as an output, and a first capacitor having one electrode receiving an output clock signal of the amplitude converting circuit and another electrode connected to the input electrode of the transistor. Therefore, the resistance of the transistor can be reduced compared with the conventional device where the potential of the input electrode of the transistor is increased or decreased solely by the power supply voltage and electric charge can efficiently be transferred. In addition, positive or negative charge of the input electrode of the transistor do not flow back to the input node when the potential of the input electrode of the transistor is increased or decreased. Hence, the resistance of the transistor can be reduced and the efficient charge transfer is allowed.
Preferably, the predetermined voltage is twice as high as the power supply voltage, and the amplitude converting circuit includes a second capacitor, a charge circuit charging the second capacitor to the power supply voltage by supplying power supply potential to one electrode of the second capacitor and supplying a ground potential to another electrode of the second capacitor during a time period in which the reference clock signal is at the second or first potential, and a second switching circuit supplying the power supply potential to another electrode of the second capacitor and connecting one electrode of the second capacitor to one electrode of the first capacitor during a time period in which the reference clock signal is at the first or second potential, and, supplying the ground potential to one electrode of the first capacitor during a time period in which the reference clock signal is at the second or first potential. In this case, the potential of the input electrode of the first transistor can be increased or decreased by an amount corresponding to twice the power supply voltage. Hence the resistance of the first transistor can sufficiently be lowered.
Further preferably, the amplitude converting circuit includes an internal charge pump circuit supplying positive charge to an internal power supply node, a control circuit controlling the charge pump circuit so as to turn a potential of the internal power supply node to a predetermined reference potential, and a second switching circuit connecting one electrode of the first capacitor to the internal power supply node during a time period in which the reference clock signal is at the first or second potential and supplying the ground potential to one electrode of the first capacitor during a time period in which the reference clock signal is at the second or first potential. In this case, the potential of the input electrode of the transistor can be increased or decreased by a desired amount by setting the reference potential at a desired level. Hence, the resistance of the first transistor can sufficiently be lowered.
Still preferably, the charge pump circuit is provided in a non-volatile semiconductor memory device. In this case, even with the decrease in a power supply voltage of the non-volatile semiconductor memory device, a high voltage can easily be generated.